1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device including a test circuit and a redundant circuit for a memory circuit, and having a function to supply information about the presence or absence of a fault and about fault remediableness.
2. Description of Related Art
One of conventional semiconductor integrated circuit devices including a test circuit and a redundant circuit is disclosed in Japanese patent application laid-open No. 8-94718 (1996).
FIG. 10 is circuit diagram showing a scan flip-flop for RAM test in a conventional semiconductor integrated circuit device disclosed in the foregoing Japanese patent application laid-open No. 8-94718 (1996). In FIG. 10, the reference numeral 100 designates a scan flip-flop (SFF), 101 designates a comparator for comparing data output from a RAM including a plurality of memory cells with a preset expected value, and for outputting a compared result.
FIG. 11 is a circuit diagram showing a RAM with a test circuit in a conventional semiconductor integrated circuit device. In FIG. 11, the reference numeral 111 designates a RAM consisting of a plurality of memory cells. Outputs DO less than  greater than  of the RAM 111 are connected to five scan flip-flops (SFFs) 100 connected in series. The five scan flip-flops (SFFs) 100 connected in series constitute a scan path circuit for testing the RAM 111.
FIG. 12 is a circuit diagram showing a conventional semiconductor integrated circuit device with a RAM 121 combined with a redundant circuit 122. The RAM 121 is a 5-bit RAM with a test circuit consisting of the RAM 111 and the five scan flip-flops (SFFs) 100 connected in series to constitute a scan path circuit as shown in FIG. 11. In FIG. 12, the reference numeral 123 designates a register for loading and storing the output data SO less than i+1 greater than xe2x88x92SO less than i+4 greater than  from the scan flip-flops (SFFs) 100. The RAM 121 of the semiconductor integrated circuit device with a test circuit supplies the register 123 with 5-bit data output signals SO less than i greater than , SO less than i+1 greater than , SO less than i+2 greater than , SO less than i+3 greater than  and SO less than i+4 greater than .
Next, the operation of the conventional device will be described.
First, a test operation will be described for the RAM 111 with five scan flip-flops (SFFS) 100 constituting the scan path circuit as shown in FIG. 11.
Before carrying out the operation test of the RAM 111, which is a memory circuit including a plurality of memory cells, that is, a plurality of bits, a control signal TM and a control signal SM are set at TM=0 and SM=1, and data xe2x80x9c1xe2x80x9d is shifted in from the SIDO terminal of the first scan flip-flop (SFF) 100. For example, the five bit scan path circuit as shown in FIG. 11 requires five clock pulses. As a result, the outputs of the scan flip-flops (SFFs) 100 are placed at SO less than i greater than =1, SO less than i+1 greater than =1, SO less than i+2 greater than =1, SO less than i+3 greater than =1 and SO less than i+4 greater than =1.
Subsequently, a test of the entire addresses of the RAM 111 is performed with placing the control signals at TM=1 and SM=1. During writing and reading of the test data to and from the RAM 111, expected values EXP and a comparison control signal CMP (compare when xe2x80x9c1xe2x80x9d) are controlled.
If a fault takes place in the RAM 111 while the comparison control signal CMP=1, the output DO less than  greater than  of the RAM 111 associated with the fault will differ from its expected value EXP, and hence the output signal from the comparator 101 will be xe2x80x9c0xe2x80x9d. Thus, the output SO of the scan flip-flop (SFF) becomes xe2x80x9c0xe2x80x9d in synchronism with a clock signal T. For example, if a fault occurs in the bit DO less than i+2 greater than  of the RAM 111, the fault is detected at the scan flip-flop (SFF)  less than i+2 greater than  100 corresponding to the bit, and the output SO less than i+2 greater than  of the scan flip-flop (SFF)  less than i+2 greater than  100 becomes xe2x80x9c0xe2x80x9d. In this case, the remaining scan flip-flops (SFFs) 100 maintain their outputs at xe2x80x9c1xe2x80x9d, and produces them as the outputs SO less than i greater than , SO less than i+1 greater than , SO less than i+3 greater than  and SO less than i+4 greater than .
After that, while the control signals are placed at TM=0 and SM=1, the test result is shifted out from the terminal SODO less than i greater than  of the final scan flip-flop (SFF) 100.
Next, the operation will be described of the RAM 121 with a test circuit including a redundant circuit 122. The semiconductor integrated circuit device as shown in FIG. 12 includes the redundant circuit 122 in connection with the RAM 121 with the test circuit as shown in FIG. 11. For example, if a bit fault is detected at the scan flip-flop (SFF)  less than i+2 greater than  100 corresponding to the output DO less than i+2 greater than  of the RAM 121, the output SO less than i+2 greater than  of that scan flip-flop (SFF) 100 becomes xe2x80x9c0xe2x80x9d. In this case, the remaining scan flip-flops (SFFs) 100 produce xe2x80x9c1xe2x80x9d as their outputs SO less than i greater than , SO less than i+1 greater than , SO less than i+3 greater than  and SO less than i+4 greater than .
Loading the outputs SO less than i+1 greater than xe2x88x92SO less than i+4 greater than  from the scan flip-flops (SFFs) 100, the register 123 produces xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d and xe2x80x9c1xe2x80x9d as its outputs G less than i+1 greater than xe2x88x92G less than i+4 greater than , respectively. Thus, the outputs of logic gates 1221, 1222 and 1223 in the redundant circuit 122 will be F less than i+3 greater than =1, F less than i+2 greater than =0 and F less than i+1 greater than =0, respectively.
As a result, the output value DO less than i+4 greater than /Q less than i+4 greater than  of the RAM 121 becomes the output value XDO less than i+3 greater than  of the redundant circuit 122. Likewise, DO less than i+3 greater than /Q less than i+3 greater than  becomes XDO less than i+2 greater than , DO less than i+1 greater than /Q less than i+1 greater than  becomes XDO less than i+1 greater than  and DO less than i greater than /Q less than i greater than becomes XDO less than i greater than , thus eliminating the output value DO less than i+2 greater than  corresponding to the fault bit.
In much the same fashion, the input value XDI less than i+3 greater than  to the redundant circuit 122 becomes the input value DI less than i+4 greater than  to the RAM 121. Likewise, XDI less than i+2 greater than  becomes DI less than i+3 greater than , XDI less than i+1 greater than  becomes DI less than i+2 greater than  and DI less than i+1 greater than , and XDI less than i greater than  becomes DI less than i greater than .
As a result, even if a bit error takes place in the memory cell corresponding to the output DO less than i+2 greater than , for example, the RAM 121 functions as a 4-bit input/output RAM because of a connecting/switching operation in the redundant circuit 122. However, if a two or more bit fault takes place in the data outputs DO less than  greater than  of the RAM 121, a fault remedial processing using the foregoing redundant circuit 122 cannot be applied.
With such an arrangement, the foregoing conventional semiconductor integrated circuit device has a problem of taking a long time for carrying out the fault test of a plurality of memory cells constituting the semiconductor integrated circuit device. This is because to achieve the fault remedial processing, it is necessary to decide as to whether two or more pieces of fault information (value xe2x80x9c0xe2x80x9d in the foregoing example) are present in the test result shifted out from the SODO less than i greater than , and this requires an external test device such as an LSI tester (not shown in the drawings) for making the decision.
The present invention is implemented to solve the foregoing problem. It is therefore an object of the present invention to provide a semiconductor integrated circuit device capable of reducing the time required for the test for the presence or absence of a fault of memory cells and for the fault remediableness. This is implemented by making a comparison and decision within the semiconductor integrated circuit device as to whether any fault information is present or not in the plurality of memory cells in the semiconductor integrated circuit device, and by outputting comparison and decision result to facilitate a fault decision processing and fault remedial processing by an external test instrument like an LSI tester.
According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: at least one memory circuit that includes a plurality of memory cells for storing data, a redundant circuit provided for the plurality of memory cells, and a scan path circuit for comparing output data of the plurality of memory cells with a set of predetermined expected values and for outputting compared result information by serially shifting out compared results; and at least one first detector for loading the compared result information serially output from the scan path circuit of the memory circuit, for detecting whether at least one piece of mismatch information is included in the compared result information, and for outputting a detection result.
Here, the semiconductor integrated circuit device may further comprise at least one second detector for loading the compared result information serially output from the scan path circuit, for detecting whether at least two pieces of mismatch information is present in the compared result information, and for outputting a detection result.
The at least one memory circuit may include a plurality of memory circuits, the at least one first detector may include a plurality of first detectors, and the at least one second detector may include a plurality of second detectors, wherein the semiconductor integrated circuit device may further comprise a first scan path circuit for loading outputs of the plurality of first detectors and for shifting them out, and a second scan path circuit for loading outputs of the plurality of second detectors and for shifting them out.
The at least one memory circuit may include a plurality of memory circuits, the at least one first detector may, include a plurality of first detectors, and the at least one second detector may include a plurality of second detectors, wherein the semiconductor integrated circuit device may further comprise: a plurality of selectors, provided for the plurality of first detectors and the plurality of second detectors, for selecting one of a set of the outputs of the plurality of first detectors and a set of the outputs of the plurality of second detectors and for outputting the set selected; and a third scan path circuit for loading the set selected by the plurality of selectors, and for serially shifting it out.
The at least one memory circuit may be a mutliport memory circuit that has n data output ports that are accessible independently, where n is an integer greater than one, the redundant circuit may be provided for the mutliport memory cells in the mutliport memory circuit, and the scan path circuit may be provided for each of k data output ports of the n data output ports, where k is an integer greater than one and less than or equal to n, and i-th scan path circuit compares output data from i-th data output port with i-th set of predetermined expected values and serially shifts out a plurality of compared results, where i is an integer from one to k, wherein the semiconductor integrated circuit device may further comprise an AND circuit for ANDing the serial outputs from the scan path circuits, and wherein the at least one first detector may detect whether the output of the AND circuit includes at least one piece of mismatch information, and output a detection result.
The semiconductor integrated circuit device may further comprise a second detector for detecting whether at least two pieces of mismatch information is present in the output of the AND circuit, and for outputting a detection result.
According to a second aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a memory circuit that includes a plurality of memory cells for storing data, a redundant circuit provided for the plurality of memory cells, and a scan path circuit for comparing output data of the plurality of memory cells with a set of predetermined expected values and for outputting compared result information by serially shifting out compared results; and a counter circuit for loading the compared result information serially output from the scan path circuit, and for counting a number of pieces of mismatch information in the compared result information.
According to a third aspect of the present invention, there is provided a semiconductor integrated circuit device comprising a memory circuit including: a plurality of memory cells for storing data; a redundant circuit provided for the plurality of memory cells; a scan path circuit for comparing output data of the plurality of memory cells with a set of predetermined expected values and for outputting compared result information by serially shifting out compared results; and a selector for supplying the scan path circuit with the compared result information serially output from the scan path circuit.